The present invention relates to a semiconductor integrated circuit device (hereinafter also called simply a xe2x80x9csemiconductor integrated circuitxe2x80x9d), and specifically to a semiconductor integrated circuit (hereinafter also called simply a xe2x80x9cflip-chip type semiconductor integrated circuitxe2x80x9d) in which protruding electrodes (hereinafter also called simply xe2x80x9cbump electrodesxe2x80x9d) such as solder bumps or the like used for circuit substrate mounting are formed on a semiconductor substrate. The present invention relates particularly to a structure of a flip-chip type semiconductor integrated circuit in which attention has been directed toward a probe test, and a manufacturing method thereof, and relates to, for example, a technology effective for application to a system LSI or the like mixed with a memory and a logical circuit or the like, and a manufacturing method thereof.
Further, the present invention relates to a semiconductor integrated circuit wherein protruding electrodes (hereinafter also called simply xe2x80x9cbump electrodesxe2x80x9d) such as solder bumps or the like for circuit substrate implementation are formed on a semiconductor substrate and program elements each of which permanently or irreversibly changes the function of a predetermined portion of the semiconductor integrated circuit, are installed thereon.
The following references are known as examples of references each of which has described a semiconductor integrated circuit having bump electrodes used for circuit substrate implementation.
(a) Unexamined Patent Publication Hei 5(1993)-218042, (b) Unexamined Patent Publication Hei 8(1996)-250498 and (c) U.S. Pat. No. 5,547,740 respectively show one basic form of a flip-chip type semiconductor integrated circuit mentioned in the present specification. Namely, the flip-chip type semiconductor integrated circuit is configured as follows. For example, relocation wirings are routed from bonding pads of its chip, bump electrodes respectively connected to the relocation wirings are laid out on the surface of the chip in array form (in area array form), and the bump electrodes arranged in area array form are exposed from a surface protection film. It is thus possible to enlarge the interval between the bump electrodes, facilitate substrate mounting that the bump electrodes are respectively connected to wirings for a printed circuit board and utilize a low-cost printed circuit board in which wiring intervals are wide.
In the flip-chip type semiconductor integrated circuit, the bump electrodes are terminals capable of being directly mounted or implemented on a circuit substrate and are equivalent to external connecting terminals such as lead pins or the like for a package. After the bump electrodes are formed and wafer processes are all completed, only the bump electrodes are exposed and the bonding pads are finally covered with an insulating film or a protection film.
The present inventors have compared the number of the bonding pads in the semiconductor chip with the number of the external terminals (bump electrodes) typified by the lead pins for the package. According to the comparison, bonding pads used only for probe inspection and bonding pads connected to power terminals or the like by a technique for a bonding option are not assigned external terminals dedicated therefor. Thus, when the flip-chip type semiconductor integrated circuit is substituted for the semiconductor integrated circuit, a wafer probe test can be performed through the use of all bonding pads if it is antecedent to the formation of the relocation wirings and bump electrodes. However, it has been found out by the present inventors that there is a fear that when a probe is brought into direct contact with each bonding pad, the bonding pad is endamaged and a failure in connection to each relocation wiring occurs.
Techniques for probe testing are not described in the References (a) through (c) at all. The technology of forming under bump metals or metallurgies on bonding pads after having been subjected to probe testing or inspection, has been described in, for example, (d) Michael J. Varnau: xe2x80x9cImpact of Wafer Probe Damage on Flip Chip Yields and Reliabilityxe2x80x9d, International Electronics and Manufacturing Technology Symposium (Oct. 23-24, 1996) as a reference in which the relation to the probe inspection has been described. As to the reference described in the paragraph (d), however, there is a possibility that when a probe is applied to one of bonding pads antecedent to a relocation wiring process, the surface of the bonding pad will damage and the reliability of connection to a relocation wiring layer will be degraded, as discussed above by the present inventors. A limitation is imposed on the selection of a relocation wiring material.
Further, the following References are known as to the probe tests performed in the flip-chip type semiconductor integrated circuit.
(e) The technology of applying a probe to each under bump metal or metallurgy (UBM) antecedent to the formation of bump electrodes to perform a probe test has been described in U.S. Pat. No. 5,597,737.
(f) A configuration wherein testing pads are provided so as to adjoin under bump metallurgies and be connected thereto, has been shown in Unexamined Patent Publication No. Hei 8(1996)-64633. The testing pads are respectively provided at the sides of bump electrodes.
(g) Unexamined Patent Publication No. Hei 8(1996)-340029 shows a description related to the invention wherein portions directly above bonding pads at which relocation wiring layers are formed, are exposed and testing pads for probe inspection are formed at their exposed portions.
(h) Unexamined Patent Publication No. Hei 8(1996)-29451 shows a description related to the invention wherein each of pads for probe testing is formed by a relocation wiring layer in the neighborhood of each bonding pad.
The present inventors could obtain the following results by further discussing the technologies described in the References referred to above.
It has been revealed by the present inventors that the technology described in the paragraph (e) also has the possibility that each under solder bump metallurgy will be endamaged at a probe tip in a manner similar to the technology described in the paragraph (d), and has led to degradation in wettability relative to solder and degradation in reliability of connections to each solder bump electrode due to the damage of a barrier metal used for the prevention of solder diffusion.
Further, the under bump metallurgies are placed in area array form in a manner similar to the bump electrodes in the technology described in the paragraph (e). In the technology described in the paragraph (f), the testing pads are also laid out in area array form together with the bump electrodes. Therefore, it has been revealed by the present inventors that each of the technologies described in the References (e) and (f) has a new problem in that it is difficult to apply a normally-used cantilever type probe to under bump metallurgies or testing pads arranged in a multiple row, and terminal-dedicated expensive probes disposed in area array form are additionally required.
It has been found out by the present inventors that the Reference described in the paragraph (g) has a problem in that when the size of each bonding pad and the interval between the bonding pads become narrow with high integration of a semiconductor device, the sizes of the testing pads and the interval therebetween become also narrow, and the positioning of each probe and reliable contact thereof fall into difficulties.
It has been revealed by the present inventors that the technology described in the paragraph (h) has the fear that since the area of each testing pad is added to its corresponding relocation wiring layer, the capacitance of a wiring increases and the electrical characteristic of a semiconductor integrated circuit is degraded.
It has been revealed by the present inventors that each of the References described in the paragraphs (f) through (h) is accompanied by a problem that since the testing pads are formed on an inorganic insulating layer or a metal wiring layer, the surface of each testing pad is hard to deform where a hard metal film such as chromium, nickel or the like is used for the testing pads, and hence the contactability with a probe tip is poor, and an expensive probe whose tip is given gold plating and which has adopted a structure capable of obtaining a wide contact area, is required.
Further, as described as the prior arts in the paragraphs (e) through (h), a problem has been revealed that when the probe is applied to the already-formed solder bump, the probe is applied to a curved surface covered with a thick oxide film under a strong load, whereby the bump is apt to deform and the probe per se is easy to undergo damage.
While the aforementioned References have described the flip-chip type semiconductor integrated circuit and the testing pads paired with the bump electrodes in this way, they do not show any description or suggestion that has taken into consideration the fact that the bonding pads used only for probe inspection and the bonding pads or the like connected to the power terminals or the like by the technique for the bonding option are not assigned the external terminals like the lead pins dedicated therefor as firstly discussed by the present inventors. Namely, the prior arts do not lead to the provision of the inventive concept that focused attention on the testing pads dedicated for testing, which are used only for probe testing or inspection and unnecessary at the final product stage. The testing pads always exist so as to pair with the bump electrodes. In other words, signals necessary for testing are set on the precondition that they are capable of being taken from the bump electrodes. Thus, the present inventors have revealed that if the solder bump electrodes are provided even for signal terminals necessary only for testing, then the number of the bump electrodes increases and the layout of the bump electrodes at practical intervals falls into difficulties from the meaning of mounting thereof to a circuit substrate.
An object of the present invention is to provide a semiconductor integrated circuit capable of executing a probe test without damage to pads antecedent to a relocation wiring process and without an increase in the number of bumps, and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor integrated circuit capable of reducing an increase in capacitance of each wiring, which is caused by the addition of a testing pad, and a manufacturing method thereof.
A further object of the present invention is to provide a semiconductor integrated circuit capable of enhancing contactability of a probe with each of testing pads, and a manufacturing method thereof.
A still further object of the present invention is to provide a semiconductor integrated circuit capable of improving reliability of connections to a printed circuit board and reducing substrate mounting costs because a bump-to-bump interval can be taken wide, and a manufacturing method thereof.
A still further object of the present invention is to provide a semiconductor integrated circuit capable of reducing capacitive loads developed by metallic wirings for laying out protruding electrodes in array form.
The present inventors have discussed even a program element together with the flip-chip type semiconductor integrated circuit. In a semiconductor integrated circuit, the program element is used for relief or the like for substitution of a defective or faulty circuit portion thereof with a redundant circuit. As the program element, a fuse comprised of, for example, a metal film or a polysilicon film is heavily used and programmed by the melting thereof by irradiation with laser light. A program relative to the fuse is executed after the completion of a probe test. In this stage, openings for exposing bonding pads and fuses have been defined in a passivation film on the surface of a wafer. For example, the probe test is carried out by using the bonding pad, for example. The laser light is selectively applied to each fuse in such a manner that the location of a defect is found out upon the probe test and the defective portion is substitutable with a relieving circuit, whereby the program for the fuse is carried out.
An electric fuse is known as another program element. For example, U.S. Pat. No. 5,110,754 has described a technology wherein an antifuse corresponding to a kind of electric fuse is used for defective relief or the like of a DRAM. The antifuse has a configuration capable of being programmed by dielectric breakdown of an oxide film held in an insulating state. Further, U.S. Pat. No. 5,742,555 has shown, as an example of an antifuse, an example in which an oxide film is used to form a capacitor in a p-type well region, and a negative voltage is applied to a well electrode of the capacitor and a positive voltage is applied to a plate electrode on the oxide film to thereby bring a gate oxide film into dielectric breakdown. As other references each having described a semiconductor integrated circuit using an electric fuse, there are known U.S. Pat. No. 5,324,681, etc.
As other program elements, there are known non-volatile storage elements each capable of reversibly changing a programmed state, such as an electrically erasable programmable EEPROM, a flash memory, etc. U.S. Pat. No. 5,742,555 has described a DRAM having such a program element.
The present inventors have discussed the mounting program elements in the flip-chip type semiconductor integrated circuit for the purpose of defective relief, mode setting and trimming.
The firstly-discussed program element is a fuse capable of being blown by laser. A fuse (polysilicon fuse) comprised of a polysilicon film is shaped in rectangular form over an element isolating region provided in a well region on a semiconductor substrate. One end of the fuse is connected to a source region of a selection transistor through metal wirings corresponding to plural layers, whereas the other end thereof is connected to a ground potential through its corresponding metal wiring. After an interlayer dielectric and a passivation film between the metal wirings corresponding to the plural layers are layered over the polysilicon fuse, the layered film is etched to define an irradiation window for the radiation of laser light and finally an insulating film having a thickness of 0.5 xcexcm to 1 xcexcm is left. When the polysilicon fuse configured in this way is blown, the laser light is applied thereto through the insulating film. For example, the width of the polysilicon film, a layout interval, and the width of the irradiation window for applying the laser light are designed so as to take 2 xcexcm, 5 xcexcm an 10 xcexcm respectively. Applying Hexe2x80x94Ne laser having an intensity of 1.5 xcexcJ and a spot diameter of 6 xcexcm at this time enables the polysilicon fuse to be blown.
It has however been revealed by the present inventors that the system for blowing the conventional polysilicon fuse by the radiation of laser light has the following problems.
The first problem is that the process of defining the window for applying the laser light therethrough is becoming very difficult. In a so-called system LSI product in which a large-capacity DRAM or the like is mixed with a high-speed logic circuit and an analog circuit, which have recently been progress on rapid market expansion in particular, the logic circuit needs to have metal wiring layers of five layers or more. Thus, since the thickness of the insulating film from the polysilicon fuse to the top passivation film reaches 5 xcexcm or more, it is technically difficult to uniformly effect etching for leaving the insulating film to a thickness of about 0.5 xcexcm at a fuse upper portion on the whole surface of the wafer. When the thickness of the insulating film at the fuse upper portion is left 1 xcexcm or more, the incident intensity of laser light becomes weak and the melting-down or blowing of the fuse becomes insufficient. When the thickness of the insulating film at the fuse upper portion is thinned to 0.5 xcexcm or less, there is in danger of the surface of the fuse being exposed depending on variations in the subsequent process treatment. Thus, the probability of failure occurrence that non-blown fuses will break, becomes high significantly.
The second problem is that the fuse cannot be blown by the conventional radiation of laser light from the viewpoint of the system of the manufacturing process in the flip-chip type semiconductor integrated circuit. In the conventional manufacturing process, a manufacturing process executed within a clean room in a wafer state is completed in a stage in which the formation of the passivation film for preventing moisture from entering an upper portion of each metal wiring layer has been completed. Afterwards, the assembly into a package is done after probe tests and relief have been carried out, followed by execution of the final selection. In the flip-chip type semiconductor integrated circuit on the other hand, the process from the formation of each metal wiring (relocation wiring) similar to a lead frame to the deposition of solder bump electrodes is carried out within the clean room in the wafer state after the formation of the passivation film in order to further reduce the manufacturing cost thereof. When the conventional system for blowing the fuse through the radiation of the laser light is applied to the flip-chip type semiconductor integrated circuit, the deposition and processing of each metal wiring for constituting the relocation wring similar to the lead frame at the upper portion of each blown fuse are performed, thereby resulting in unavoidance of degradation in reliability due to the corrosion of the polysilicon fuse and entrance of moisture from its corroded portion. Thus, the present inventors have found out the need for a system capable of electrically performing some kind of program in the flip-chip type semiconductor integrated circuit as an alternative to the system for blowing the fuse by the radiation of the laser light.
The third problem resides in that the polysilicon fuse needs a relatively large layout area. One fuse needs a layout area of at least 5xc3x9710 xcexcm2. This becomes a big factor that determines the upper limit of the number of fuses.
Next, the present inventors have discussed even the adoption of an electrically writable and erasable non-volatile storage element as the program element. According to it, it has been revealed that when the number of the program elements may be low, a chip occupied area taken by peripheral circuits used for electrical writing or the like relatively increases and hence area efficiency becomes disadvantageous.
According to the result of discussions, the present inventors have found out superiority in adoption of the electric fuse such as the antifuse or the like as the program element for the flip-chip type semiconductor integrated circuit. At this time, the present inventors have further revealed that since the application of a voltage for dielectric breakdown to the antifuse is a process necessary only in manufacturing stage of the semiconductor integrated circuit, there is no room to provide dedicated bump electrodes for the purpose of dielectric breakdown under such circumstances that a large number of bump electrodes must be formed with a great increase in the scale of the semiconductor integrated circuit. Further, since the state of stress/distortion developed in the bump electrodes is transferred directly to a chip because the bump electrodes are used as terminals for circuit board mounting in the flip-chip type semiconductor integrated circuit, the present inventors have recognized the need for the provision of means for relaxing it.
The present inventors have further discussed a bonding option for the flip-chip type semiconductor integrated circuit from another standpoint. The bonding option is a technique for determining operation modes according to, for example, whether each of bonding pads assigned to operation mode setting electrodes of a semiconductor integrated circuit, for example, should be kept floating or connected to a power terminal. To which lead pin a predetermined bonding pad of a semiconductor chip should be bonded, may be selected upon assembly in the bonding option. However, the bump electrodes are used as the terminals mounted directly to the circuit substrate or board in the flip-chip type semiconductor integrated circuit and correspond to the lead pins for the package. Thus, the execution of the process like the bonding option is no longer physically impossible after wafer processes are all completed. In order to change each of bump electrodes to be connected to electrode pads like specific bonding pads, wiring patterns each extending from the electrode pad like the predetermined bonding pad to its corresponding bump electrode must individually be changed. On the other hand, the present inventors have taken recognition of a need to enable a flip-chip type semiconductor integrated circuit having completed such wiring patterns once to be functionally set subsequently with a view toward gaining versatility or usability equivalent to the bonding option.
An object of the present invention is to provide a flip-chip type semiconductor integrated circuit which does not give rise to degradation in reliability elicited by using a by-laser fusible fuse as a program element, and a method of manufacturing the same.
Another object of the present invention is to provide a semiconductor integrated circuit wherein electrodes required to electrically change the state of a program element employed in a flip-chip type semiconductor integrated circuit do not limit the number of protruding electrodes for other applications.
A further object of the present invention is to provide a semiconductor integrated circuit capable of relaxing the state of stress/distortion given to a semiconductor substrate through protruding electrodes in a flip-chip type semiconductor integrated circuit.
A still further object of the present invention is to provide a flip-chip type semiconductor integrated circuit capable of easily obtaining versatility equivalent to a bonding option with respect to function setting or the like, and a method of manufacturing the same.
A still further object of the present invention is to provide a manufacturing method of efficiently carrying out necessary function selection and relief accompanied by inspection and a change in the state of a program element to thereby allow the manufacture of a flip-chip type semiconductor integrated circuit.
The above, other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described as follows:
 less than  less than Probe Test and Flip-chip Type Semiconductor Integrated Circuit greater than  greater than 
[1] In the invention related to a flip-chip type semiconductor integrated circuit having focused attention on a probe test, testing pads (209b) each using a conductive layer such as a relocation wiring layer (205) or an under bump metallurgy layer (207) or the like are provided just above or in the neighborhood of terminals (202b) like bonding pads, which are not provided with bump electrodes (208) thereat and are used only for probe testing. Similar testing pads (209a) may be provided even with respect to terminals (202a) like bonding pads at which the bump electrodes are provided. The probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
Further, conductive layers like relocation wirings 205), and testing pads (209a, 209b) are formed on an organic insulating layer (204) such as polyimide or the like. Owing to the provision of the testing pads on the organic insulating layer low in dielectric constant and easy to increase its thickness, the capacitance between each of the testing pads and a semiconductor circuit placed therebelow can be reduced. Since the modulus of elasticity of the organic insulating layer is relatively low, the surface of each testing pad is easy to deform and hence contactability of each probe is enhanced.
An insulating layer (206) is formed on the relocation wiring. An under bump metallurgy and testing pads are formed thereon. Thus, the provision of each testing pad on the layered insulating layers corresponding to the two layers placed above and below the relocation wiring makes it possible to reduce the capacitance between each testing pad and the semiconductor circuit placed therebelow.
[2] The above will further be explained in detail. The testing pads (209b) are provided exclusively to the bump electrodes (208). Thus, the layout of the bump electrodes at practical intervals can be facilitated to the fullest extent from the meaning of the mounting thereof to a circuit substrate. Namely, a semiconductor integrated circuit device comprises a semiconductor substrate, a plurality of circuit elements formed in an element forming layer on the semiconductor substrate, a plurality of terminals (202a, 202b) formed on the surface of the element forming layer and connected to the predetermined circuit elements, a plurality of conductive layers (205) which are respectively connected to first terminals (202a) corresponding to some terminals of the plurality of terminals and extend on the element forming layer, protruding electrodes (208) respectively connected to the conductive layers, testing pads (209b) respectively connected to all or some of second terminals (202b) corresponding to the remaining terminals of the plurality of terminals, and an insulating film (206) which covers the surfaces of the protruding electrodes and the testing pads so as to expose the protruding electrodes and the testing pads.
In the above, testing pads (209a) can be added to the terminals (202a) each having the protruding electrode (208). A wafer probe test can easily be carried out using the testing pads (209a, 209b) alone.
When the conductive layers are used as relocation wirings (205) for protruding electrodes with respect to the arrangement of the terminals, the insulating films (204, 206) are disposed above and below each of the conductive layers. The insulating films relax the state of stress/distortion given to the semiconductor substrate through the protruding electrodes and testing pads in the flip-chip type semiconductor integrated circuit. If a film containing an organic material such as a polyimide film, a fluorocarbon resin film, or an elastomer film which contains a silicon or acrylic rubber material, is used as the insulating films in particular, then the film is relatively low in the modulus of elasticity as compared with an insulating film such as a silicon oxide film or the like, it is suited for the relaxation of the state of stress/distortion.
The testing pads can be placed just above the terminals corresponding thereto. Further, the testing pads can regularly be placed in the central portion of the semiconductor substrate, and the protruding electrodes can regularly be placed outside the testing pads respectively. The testing pads can also be extended on its corresponding insulating film.
[3] A method of manufacturing a semiconductor integrated circuit having a structure wherein the testing pads are provided exclusively to protruding electrodes, includes a first step (FIGS. 37 through 40) for constituting a required circuit in an element forming layer on a semiconductor wafer, forming a plurality of terminals (202a, 202b) connected to the predetermined circuit elements on the surface of the element forming inlayer, and causing a plurality of conductive layers (205) to be respectively connected to first terminals (202a) corresponding to some of the plurality of terminals and to extend over the element forming layer, a second step (FIG. 43) for forming protruding electrodes (208) connected to the conductive layers, a third step (FIG. 41) for connecting testing pads (209b) to all or some of second terminals (202b) corresponding to the remaining terminals of the plurality of terminals respectively to form the testing pads, a fourth step (FIG. 42) for inspecting the required circuit formed in the element forming layer, a fifth step (S9 in FIG. 58) for performing burn-in, and a sixth step (S8 in FIG. 58) for dicing the wafer.
When testing pads (209a) are added even to the terminals (202a) each having the protruding electrode (208), the thirst step results in a process for connecting all or some of the second terminals and all or some of the first terminals respectively to thereby form the testing pads.
Burn-in is performed after the execution of dicing posterior to the formation of protruding electrodes. Alternatively, the protruding electrodes are formed after burn-in in reverse and dicing may be carried out. In the former, burn-in sockets prepared for a BGA (Ball Grid Array) type semiconductor chip in which external connecting electrodes are mapped in area array form, can be used appropriately in a manner similar to the flip-chip type semiconductor integrated circuit. Alternatively, the arrangement of protruding electrodes in area array form is matched with the arrangement of the terminals for the existing burn-in sockets, whereby custom-engineered burn-in sockets may not be prepared newly and burn-in in each chip unit can easily be performed. This contributes even to a reduction in test cost. In the latter, the burn-in can also be carried out by using testing pads or testing pads and an under bump metallurgy as well as a probe test. Thus, contacting with each socket under a high temperature makes it possible to prevent the deformation of protruding electrodes like solder bump electrodes.
 less than  less than Program Element and Flip-chip Type Semiconductor Integrated Circuit greater than  greater than 
[4] In the present invention, a program element (1) like an electric fuse is adopted for a flip-chip type semiconductor integrated circuit. Namely, the semiconductor integrated circuit includes a semiconductor substrate (10), a plurality of circuit elements (1, 2) formed in an element forming layer (semiconductor region, circuit element forming region including wiring layer and insulating layer) on the semiconductor substrate, a plurality of terminals (86, 87, 88, 89) formed on the surface of the element forming layer and connected to the predetermined circuit elements, conductive layers (90) which are connected to the predetermined terminals (86, 87, 88, 89) and extend on the element forming layer, and protruding electrodes (93) connected to the conductive layers. At this time, a program element (1) for irreversibly changing a high-resistance state or a low-resistance state of a current path or channel by the development of a predetermined potential difference in the current channel is provided as at least one of the circuit elements. At least one of the terminals is defined as voltage input terminals (86, 87) for forming the potential difference.
According to the above, elicited degradation in reliability is not developed at all owing to the use of a laser-fusible fuse as the program element.
When the conductive layers are used as the relocation wirings (205) for the protruding electrodes with respect to the arrangement of the terminals, insulating films (204, 206), which expose at least the protruding electrodes and cover the surface thereof, can be placed above and below each of the conductive layers. Owing to such insulating films, the state of stress/distortion applied to the semiconductor substrate through each protruding electrode (209) in the flip-chip type semiconductor integrated circuit can be relaxed. If a polyimide film containing an organic substance or a film such as elastomer is adopted as the insulating films in particular, then the film is relatively low in the modulus of elasticity as compared with an insulating film such as silicon oxide or the like, and hence the film is excellent in the relaxation of the state of stress/distortion.
The semiconductor integrated circuit can further be provided with pad electrodes (90, 90a) which are respectively connected to the terminals and exposed from the insulating films. The pad electrodes can be used for testing pads or the like provided for the purpose of probe tests.
Some pad electrodes (90a) in the pad electrodes can be used to apply voltages for developing a predetermined potential difference in the program element. In the case of a circuit configuration in which the pad electrodes (90a) may be kept floating after the program element has been programmed, protruding electrodes may not be assigned to the pad electrodes (90a). Thus, the electrodes required to electrically change the state of the program element employed in the flip-chip type semiconductor integrated circuit do not limit the number of protruding electrodes for other applications. On the other hand, in the case of a circuit configuration in which after the program element has been programmed, the pad electrodes (90a) must forcedly be set to a ground potential (Vss) or a source voltage (Vcc), protruding electrodes (93a) are assigned to the pad electrodes (90a), and the protruding electrodes (93a) may be connected to power wrings for the ground potential (Vss) or the source voltage (Vcc) on a wiring board upon substrate implementation.
When the voltages for developing the predetermined potential difference in the program element are voltages different form operating source voltages employed in a circuit other than the program element, the electrode for applying the program voltage may be shared between a plurality of program elements.
An electric fuse changed from a high-resistance state to a low-resistance state due to an electrical breakdown can be adopted for the program element. For example, the current path or channel of the program element is charged with an insulating film in the high-resistance state, and the insulating film is broken in the low-resistance state.
The breakdown of the insulating film can be carried out by applying a positive voltage (VDD) to one end of the current channel and applying a negative voltage (Vbbxe2x80x2) to the other end thereof. Thus, the program element can obtain a high voltage as a predetermined potential difference, and an absolute value-based voltage with a circuit""s ground voltage (Vss) as the reference can be limited to a substantially normal operating voltage. In this case, the negative voltage may commonly be supplied from the protruding electrodes or pad electrodes used for application of the predetermined voltages for forming the potential difference to each individual program elements. Alternatively, an internal voltage formed inside a chip, based on a positive voltage (VDD) and a ground voltage (GND) supplied from outside the chip may be supplied to each of the program elements. For example, a high voltage (VCH) or a negative voltage (Vbbxe2x80x2) higher than the VDD is used as the internal voltage. As to the presence or absence of a program for each program element, the applied voltage on the opposite side of the program element may be controlled by use of an address signal or the like.
The program element can be used for defective relief. Namely, the semiconductor integrated circuit has normal circuits each comprised of the circuit elements and at least one relieving circuit corresponding to one to be substituted for the defective normal circuit and comprised of the circuit elements. The program elements can be adopted for memory means (160) for storing relief information for specifying the normal circuit to be replaced by the corresponding relieving circuit. For instance, the normal circuits are memory cells and the relieving circuit is a redundant memory cell. The semiconductor integrated circuit has a comparator (161) which compares the relief information stored by the corresponding program element and an access address signal of each memory cell referred to above and is comprised of the circuit elements, and a selection circuit (106XD) which is capable of selecting the redundant memory cell as an alternative to the selection of the memory cell in response to the coincidence of the comparator and capable of selecting the corresponding memory cell in response to the non-coincidence of the comparator and which comprises the circuit elements.
The program elements can be used for the function selection of the semiconductor integrated circuit. Namely, the program elements can be adopted as means (AF0 through AF2) for storing operation mode designation information for determining operation modes of the semiconductor integrated circuit. Thus, the flip-chip type semiconductor integrated circuit can easily obtain versatility equivalent to a bonding option in terms of the function selection or operation mode selection even after the formation of the protruding electrodes.
The program elements can be adopted as means (AF10 through AF12) for storing trimming information used for selecting the characteristic of a predetermined circuit incorporated in the semiconductor integrated circuit. For example, the semiconductor integrated circuit has a resistance type voltage divider (183), and the trimming information stored in the program element selects a divided voltage produced by the resistance type voltage divider.
[5] A method of manufacturing a semiconductor integrated circuit wherein program elements like electric fuses are adopted for a flip-chip type semiconductor integrated circuit, includes a first step for constituting a required circuit in an element forming layer on a semiconductor wafer, taking or including at least a program element for irreversibly changing a high-resistance state or a low-resistance state of a current path or channel by development of a predetermined potential difference in the current channel in the circuit and forming a plurality of terminals connected to the circuit on the surface of the element forming layer, a second step (S7) for forming a plurality of protruding electrodes for mounting connections, corresponding to some of the plurality of terminals, a third step (S5) for testing or inspecting the circuit, a fourth step (S6) for replacing a defective or faulty portion with a relieving circuit according to the result of inspection by the third step, a fifth step (S9) for performing burn-in, and a sixth step (S8) for dicing the wafer. Further, the method includes a seventh step (S4) for irreversibly changing the state of each of the program elements to thereby select the function of the circuit. The dielectric breakdown type electric fuse (1) can be used as the program element.
According to the above, the function selection of the semiconductor integrated circuit is allowed without using a by-laser fusible fuse as the program element. Thus, this can contribute to yield enhancement of a flip-chip type semiconductor integrated circuit subjected to the function selection and manufactured, and an improvement in reliability thereof.
The selection of each function by the program element can be carried out before the formation of the protruding electrodes. Namely, the second step (S7) is carried out after the seventh step (S4). After the formation of the protruding electrodes, irregularities are formed on the wafer to no small extent. If the function selection is done before the formation of the protruding electrodes, then the contact of a probe with each pad or terminal for the application of a voltage to the program element for the function selection is easy and the working efficiency of the function selection can be improved.
Contrary to the above, the function selecting (S4) based on the program element can be performed after the formation of the protruding electrodes (S7). In this case, it is necessary to expose electrodes for respectively applying voltages to the program elements on the surface of the semiconductor integrated circuit for the purpose of the function selection in a manner similar to the protruding electrodes. However, since each individual semiconductor integrated circuits can be stocked in a state in which each wafer process has virtually been finished, except for a process attendant on the function selection, stock management is easy.
In the fourth step (S6) for replacing the defective portion by its corresponding relieving circuit, the replacement thereof can be performed while the state of each program element is being irreversibly changed. At this time, the respective steps for the function selection (S4), inspection (S5) and relief (S6) can be carried out by one-circuit probing processing. Namely, the third step, fourth step and seventh step are sequentially performed and respectively include probing processing on the terminals or protruding electrodes as needed. If the protruding electrodes are formed (S7) after the respective steps for the function selection (S4), inspection (S5) and relief (S6), then the contact of a probe with each pad or terminal for the application of a voltage to each program element is easy and the working efficiency of the inspection and relief can also be improved as well as that of the function selection.
If the protruding electrodes are formed according to the second step after the fifth step (S9) for performing the burn-in (S7), it is then unnecessary to consider the deformation of each protruding electrode under a high-temperature environment, and hence the burn-in can easily be carried out from its standpoint.
[6] When attention is given to the replacement of a defective portion with a relieving circuit in a flip-chip type semiconductor integrated circuit, a method of manufacturing a semiconductor integrated circuit includes a first step for constituting a required circuit in an element forming layer on a semiconductor wafer, taking or including at least a program element for irreversibly changing a high-resistance state or a low-resistance state of a current path or channel by development of a predetermined potential difference in the current channel in the circuit and forming a plurality of terminals connected to the circuit on the surface of the element forming layer, a second step (S7) for forming a plurality of protruding electrodes for mounting connections, corresponding to some of the plurality of terminals, a third step (S5) for testing or inspecting the circuit, a fourth step (S6) for replacing a defective or faulty portion with a relieving circuit according to the result of inspection by the third step, a fifth step (S9) for performing burn-in, and a sixth step (S8) for dicing the wafer. The fourth step (S6) is provided as a step for irreversibly changing the state of each of the program elements to thereby perform the replacement. In the fourth step, a voltage for developing a predetermined potential difference in the current path is applied to a predetermined terminal connected to the program element, of the plurality of terminals, for example. The program element is used as the dielectric breakdown type electric fuse, for example.
According to the above, the defective relief of the semiconductor integrated circuit is allowed without using a by-laser fusible fuse as the program element. Thus, this can contribute to yield enhancement of a flip-chip type semiconductor integrated circuit manufactured under the relief, and an improvement in reliability thereof.